This invention generally relates to semiconductor fabrication and more particularly to a system of determining overlay error while inspecting a wafer-in-process to determine the accuracy of layer-to-layer alignment and/or a method for inspecting a wafer-in-process to determine line-shortening errors in a covered layer.
A common technique used to fabricate an integrated circuit on a semiconductor device is to build the integrated circuit in layers on a silicon wafer. Each layer corresponds to a process level during fabrication. The circuit pattern for each new layer must be placed upon the previous layer within a given spacial tolerance in order for the finished integrated circuit on the semiconductor device to perform its intended function. Alignment is the term used to describe the placement of one layer of a multiple layered integrated circuit with respect to the previous layers of the integrated circuit. As integrated circuit processing becomes more and more precise and the dimensions of the various circuit components become smaller, the necessity for precision alignment of each process layer to preceding process layers becomes greater.
Typically, a wafer will include alignment portions surrounding portions reserved for semiconductor artwork. During the semiconductor fabrication process, a target attribute will be formed on a lower layer of an alignment portion of a wafer-in-process at the same time as semiconductor features are formed on other portions of the layer. Subsequently, a contact attribute will be formed on an upper layer of the alignment portion at the same time as corresponding semiconductor features. The overlay error, or misalignment between the lower and upper layers, is then determined by optically measuring the differences between the target attributes and the contact attributes. Additionally or alternatively, it is sometimes necessary to determine line-shortening (or image-shortening) errors on a lower layer that is covered by an upper layer and optical measurements are also depended upon in this determination.
A significant problem in using optical measurements to determine the accuracy of alignment of one process layer to a subsequent process layer is that typically the target attribute is covered by a sputtered coating or an oxide or resist coating. As such, the target attribute may not be directly visible. This requires the overlay inspection to rely upon an interpretation of the overlying surface variation as an indicator of the boundaries of the covered attribute. Unfortunately, such overlay inspection technique may not be accurate due to location variations in the thickness of the covering or other asymmetries thereof.
Accordingly, a need remains for a method for accurately determining the degree of alignment of one process layer to a subsequent process layer during semiconductor processing regardless of asymmetric characteristics of coatings, coverings, or films. Additionally or alternatively there is a need for a method for accurately determining line-shortening errors in a lower process layer covered by an upper process layer.
The present invention provides a system and method for accurately measuring overlay misalignment during semiconductor process that is not affected by asymmetric characteristics of coatings or coverings. The system and method of the present invention relies on electrical measurements to determine the accuracy of alignment of one process layer to a subsequent process layer. In this manner, the errors commonly associated with optical measurements are eliminated.
The present invention provides a system and method for inspecting a semiconductive wafer-in-process to determine the accuracy of alignment of a lower process layer to an upper process layer. Conductive target attributes are formed on the lower process layer of a first alignment portion of the wafer-in-process and contact attributes are formed on and through the upper process layer through which an electrically conductive path can be established with the target attributes in an acceptable alignment situation but cannot be established in an unacceptable alignment situation. The contact attributes are selectively positioned along the upper process layer to cover respective regions over the lower process layer. The contacts are also selectively spaced apart from other contacts by predetermined distances respectively. The contacts and targets are mapped, and by determining which contacts provide conductive paths and which do not, the degree of overlay error can be determined.
In an embodiment, the forming steps comprise forming a series of target attributes and forming a corresponding series of contact attributes so that the contact attributes will overlay the corresponding target attributes in differing degrees in an acceptable alignment situation. The overlay arrangement may be such that the contact attributes will, in an acceptable alignment situation, overlay the corresponding target attributes in progressively differing degrees whereby the magnitude of misalignment may be determined in a nonacceptable alignment situation. Additionally or alternatively, the overlay arrangement may be such that contact attributes will overlay the corresponding target attributes in differing degrees in opposite directions in an acceptable alignment situation whereby the direction of misalignment may be determined in a nonacceptable alignment situation.
In an embodiment, the target attribute comprises at least one conductive strip and/or the contact attribute comprises at least one contact hole extending through the upper layer to the target attribute. The target attribute may comprise a plurality of conductive strips and the contact attribute may comprise at least one contact hole for each conductive strip through which an electric path can be established in an acceptable alignment situation but not in an unacceptable alignment situation. The contact attribute may comprise at least one row of contact holes for each conductive strip through which an electric path can be established in an acceptable alignment situation but not in an unacceptable alignment situation.
In an embodiment, the conductive target strips extend in a first direction x whereby the accuracy of alignment in the x direction may be determined based on whether or not an electrical path is established. The method may include the additional steps of forming conductive target strips that extend in ay direction transverse to the x direction on the lower layer on a second alignment portion of the wafer-in-process and forming rows of contact holes on the upper process layer through which an electric path can be established with the target strips on the second alignment portion in an acceptable alignment situation but not established in an unacceptable alignment situation. It is then attempted to establish an electric path from the target strips through the contact holes to determine the accuracy of alignment in the y direction based on whether or not an electrical path is established.
The present invention additionally or alternatively provides a method for accurately measuring line-shortening errors in a lower layer that is covered by an upper layer during semiconductor fabrication. This method also relies on electrical measurements rather than optical measurements. In this manner, measurements are not affected by asymmetric characteristics of coatings or coverings and errors commonly associated with optical measurements are eliminated.
In an embodiment, the present invention provides a method of inspecting a semiconductive wafer-in-process to determine line-shortening errors in a lower process layer covered by an upper process layer. The method comprises the steps of forming a conductive target attribute on the lower process layer on an alignment portion of the wafer-in-process and forming a contact attribute on the upper process layer through which an electric path can be established with the target attribute if line-shortening effect is within an acceptable range but not established if line-shortening effect is within an unacceptable range. By attempting to establish a conductive path from the target attribute through the contact attribute, the range of line-shortening effect can be determined based on whether or not an electrical path is established. In an embodiment, a series of target attributes and a corresponding series of contact attributes are formed in such a manner that the contact attributes will overlay the corresponding target attributes in differing degrees if the line shortening effects are within the acceptable range. For example, the contact attributes will, in an acceptable line-shortening situation, overlay the corresponding target attributes in progressively differing degrees whereby the magnitude of line-shortening may be determined in a nonacceptable line-shortening situation.
These and other features of the invention are fully described and particularly pointed out in the claims. The following description and drawings set forth in detail certain illustrative embodiments of the invention, these being indicative, however, of but a few of the various ways in which the principles of the invention may be employed.